The present invention relates to an arithmetic circuit which can be installed on a digital apparatus or the like, and execute high speed computation to obtain the absolute value of a distance between two input data (this distance is referred to as absolute-valued distance or is abbreviated to "AVD" hereinafter).
Recently, a variety of products which the digital processing is applied to, have been brought to market one after another. In general, for the digital processing in these products, a high speed functional unit is used to execute a high speed algorithm adopted by the product. Thus, this makes it possible to carry out a sophisticated process which can not be handled by the analog process. One of the most significant applications of the digital process is an adaptive control, which is inevitable for the process of controlling a digital telephone communication system or the like. In the typical adaptive control, a control quantity to control an object is determined in response to the magnitude of a difference (distance) between a value as estimated and a value as measured actually.
In case of computing a distance between a value as estimated and one measured actually, it is often required to compute an absolute-valued distance (AVD). Therefore, a processor for use in the digital processing, such as a Digital Signal Processor (DSP), is provided with the function capable of executing the AVD arithmetic command. This means that such processor includes a built-in AVD arithmetic circuit.
FIG. 2 is a structural view indicating an example of a conventional AVD arithmetic circuit. This AVD arithmetic circuit is a circuit for computing an absolute value of a difference .vertline..alpha.-.beta..vertline. from a minuend data .beta., and subtrahend data .beta., both data being inputted to the circuit. This circuit is provided with an inverter 1 which generates the 1's (one's) complement * .beta. of the input data .beta., and an arithmetic logical unit (referred to as ALU hereinafter) 2 having the function as an adder. The inverter 1 acts to invert the value of respective bits of the data .beta. having a predetermined bit width. The output side of the inverter 1 is connected with one of two input ports of the ALU 2. The remaining input port of the ALU 2 is arranged the data .alpha. to be inputted thereto. The ALU 2 is arranged to receive not only data * .beta., .alpha. but also the data indicating of "1."
A selector 3 for selecting one of two data and a code inverting circuit 4 are arranged on the output side of the ALU 2. The input port of the code inverting circuit 4 is connected with the ALU 2 so as to receive the output data therefrom. The code inverting circuit 4 is constituted to include an inverter (not shown) which inverts each bit of the output data from the ALU 2, and a plurality of half adders (not shown), each one input terminal of which the value of each bit outputted from the above inverter is inputted to. These half adders are arranged to be connected with each other in such a manner that "1" is inputted to one half adder corresponding to the least significant bit (referred to as LSB hereinafter) and the carry data is sequentially inputted to other half adders from the low order bit side to the high order bit side. To the selector 3 are the output data from both of the ALU 2 and the code inverting circuit 4 inputted, and at the same time, the value of the most significant bit (referred to as MSB hereinafter) of the output data from the ALU 2 are inputted as a selection signal.
In the conventional AVD arithmetic circuit, the addition of data * .beta., .alpha. and data "1" i.e. .alpha.+* .beta.+1 is executed by using the function of the ALU 2 as the adder, namely (.alpha.-.beta.) is computed. The ALU 2 makes use of the MSB to indicate whether the data (.alpha.-.beta.) is positive or negative. The code inverting circuit 4 inverts the value of each bit of the resultant data (.alpha.-.beta.) computed by the ALU 2 and then adds "1" thereto. After this, it computes (-(.alpha.-.beta.)). The selector 3 selects either data (.alpha.-.beta.) or (-(.alpha.-.beta.)) based on the MSB of the output data from the ALU 2. When the MSB is "0" which means that the resultant data is positive, the selector 3 selects the data (.alpha.-.beta.). On the contrary, when the MSB is "1" which means that the resultant data is negative, the selector 3 selects the data (-(.alpha.-.beta.)). In this way, .vertline..alpha.-.beta..vertline. is computed.